Add debug instruction

2 files changed, 18 insertions, 1 deletions

diff --git a/src/opcodes.rs b/src/opcodes.rs
index 2502782..b937386 100644
--- a/src/opcodes.rs
+++ b/src/opcodes.rs
@@ -746,7 +746,11 @@ impl GBState {
             0b011 => match n1 {
                 0b000 => self.jp16(),
                 0b001 => self.op_bitwise(), // Bitwise operations
-                0b010 | 0b011 | 0b100 | 0b101 => unimplemented!(),
+                0b011 | 0b100 | 0b101 => unimplemented!(),
+                0b010 => {
+                    self.cpu.print_debug();
+                    Ok(4)
+                },
                 0b110 => {
                     self.mem.ime = false;
                     Ok(4)
diff --git a/src/state.rs b/src/state.rs
index 49bea41..81e841d 100644
--- a/src/state.rs
+++ b/src/state.rs
@@ -83,6 +83,19 @@ impl CPU {
             _ => unimplemented!(),
         }
     }
+
+    pub fn print_debug(&self) {
+        println!(
+            "PC: 0x{:04x}, SP: 0x{:04x}, A: 0x{:02x}, BC: 0x{:04x}, DE: 0x{:04x}, HL: 0x{:04x}, F: 0x{:02x}",
+            self.pc,
+            self.sp,
+            self.r[reg::A as usize],
+            self.r16(reg::BC),
+            self.r16(reg::DE),
+            self.r16(reg::HL),
+            self.r[reg::F as usize],
+        );
+    }
 }
 
 pub struct Memory {