Add load/save parameters to the CLI & remove errors

1 files changed, 164 insertions, 164 deletions

diff --git a/src/opcodes.rs b/src/opcodes.rs
index 3779af0..a8af25f 100644
--- a/src/opcodes.rs
+++ b/src/opcodes.rs
@@ -1,35 +1,35 @@
 use crate::io::{Audio, Serial};
-use crate::state::{flag, reg, GBState, MemError};
+use crate::state::{flag, reg, GBState};
 
 // The opcodes functions are returning the number of cycles used.
 
 impl<S: Serial, A: Audio> GBState<S, A> {
-    fn r_16b_from_pc(&mut self) -> Result<u16, MemError> {
-        let p: u16 = self.mem.r(self.cpu.pc)? as u16 | ((self.mem.r(self.cpu.pc + 1)? as u16) << 8);
+    fn r_16b_from_pc(&mut self) -> u16 {
+        let p: u16 = self.mem.r(self.cpu.pc) as u16 | ((self.mem.r(self.cpu.pc + 1) as u16) << 8);
         self.cpu.pc += 2;
 
-        Ok(p)
+        p
     }
 
-    fn r_8b_from_pc(&mut self) -> Result<u8, MemError> {
-        let p = self.mem.r(self.cpu.pc)?;
+    fn r_8b_from_pc(&mut self) -> u8 {
+        let p = self.mem.r(self.cpu.pc);
         self.cpu.pc += 1;
 
-        Ok(p)
+        p
     }
 
-    fn ldrr(&mut self, n1: u8, n2: u8) -> Result<(), MemError> {
+    fn ldrr(&mut self, n1: u8, n2: u8) -> () {
         // Load a register into another register
         // LD r, r
-        self.w_reg(n1, self.r_reg(n2)?)
+        self.w_reg(n1, self.r_reg(n2))
     }
 
-    fn ldr8(&mut self, n1: u8) -> Result<u64, MemError> {
+    fn ldr8(&mut self, n1: u8) -> u64 {
         // Load an raw 8b value into a register
-        let p = self.r_8b_from_pc()?;
+        let p = self.r_8b_from_pc();
 
-        self.w_reg(n1, p)?;
-        Ok(8)
+        self.w_reg(n1, p);
+        8
     }
 
     fn ldrr16(&mut self, rr: u8, x: u16) {
@@ -37,13 +37,13 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         self.cpu.w16(rr, x);
     }
 
-    fn ldnnsp(&mut self) -> Result<u64, MemError> {
+    fn ldnnsp(&mut self) -> u64 {
         // Load SP into an arbitrary position in memory
-        let p = self.r_16b_from_pc()?;
+        let p = self.r_16b_from_pc();
 
-        self.mem.w(p, (self.cpu.sp & 0xff) as u8)?;
-        self.mem.w(p + 1, (self.cpu.sp >> 8) as u8)?;
-        Ok(20)
+        self.mem.w(p, (self.cpu.sp & 0xff) as u8);
+        self.mem.w(p + 1, (self.cpu.sp >> 8) as u8);
+        20
     }
 
     fn ldsphl(&mut self) -> u64 {
@@ -51,48 +51,48 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         8
     }
 
-    fn ldnna(&mut self, nn: u16) -> Result<(), MemError> {
+    fn ldnna(&mut self, nn: u16) -> () {
         // Load A into an arbitrary position in memory
-        self.mem.w(nn, self.cpu.r[reg::A as usize])?;
-        Ok(())
+        self.mem.w(nn, self.cpu.r[reg::A as usize]);
+        ()
     }
 
-    fn ldann(&mut self, nn: u16) -> Result<(), MemError> {
+    fn ldann(&mut self, nn: u16) -> () {
         // Load A from an arbitrary position in memory
-        self.cpu.r[reg::A as usize] = self.mem.r(nn)?;
-        Ok(())
+        self.cpu.r[reg::A as usize] = self.mem.r(nn);
+        ()
     }
 
-    pub fn push(&mut self, x: u16) -> Result<(), MemError> {
+    pub fn push(&mut self, x: u16) -> () {
         self.cpu.sp -= 2;
 
-        self.mem.w(self.cpu.sp, (x & 0xff) as u8)?;
+        self.mem.w(self.cpu.sp, (x & 0xff) as u8);
 
-        self.mem.w(self.cpu.sp + 1, (x >> 8) as u8)?;
+        self.mem.w(self.cpu.sp + 1, (x >> 8) as u8);
 
-        Ok(())
+        ()
     }
 
-    fn pop(&mut self) -> Result<u16, MemError> {
-        let res = self.mem.r(self.cpu.sp)? as u16 | ((self.mem.r(self.cpu.sp + 1)? as u16) << 8);
+    fn pop(&mut self) -> u16 {
+        let res = self.mem.r(self.cpu.sp) as u16 | ((self.mem.r(self.cpu.sp + 1) as u16) << 8);
 
         self.cpu.sp += 2;
 
-        Ok(res)
+        res
     }
 
-    fn jr8(&mut self) -> Result<u64, MemError> {
+    fn jr8(&mut self) -> u64 {
         // Unconditional relative jump
-        let p = self.r_8b_from_pc()?;
+        let p = self.r_8b_from_pc();
 
         self.cpu.pc = (self.cpu.pc as i16 + p as i8 as i16) as u16;
 
-        Ok(12)
+        12
     }
 
-    fn jrcc8(&mut self, n1: u8) -> Result<u64, MemError> {
+    fn jrcc8(&mut self, n1: u8) -> u64 {
         // Conditional relative jump
-        let p = self.r_8b_from_pc()?;
+        let p = self.r_8b_from_pc();
         let mut cycles = 8;
 
         if self.cpu.check_flag(n1 & 0b11) {
@@ -100,16 +100,16 @@ impl<S: Serial, A: Audio> GBState<S, A> {
             self.cpu.pc = (self.cpu.pc as i16 + p as i8 as i16) as u16;
         }
 
-        Ok(cycles)
+        cycles
     }
 
-    fn jp16(&mut self) -> Result<u64, MemError> {
+    fn jp16(&mut self) -> u64 {
         // Unconditional absolute jump
-        let p = self.r_16b_from_pc()?;
+        let p = self.r_16b_from_pc();
 
         self.cpu.pc = p;
 
-        Ok(16)
+        16
     }
 
     fn jphl(&mut self) -> u64 {
@@ -119,9 +119,9 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         4
     }
 
-    fn jpcc16(&mut self, n1: u8) -> Result<u64, MemError> {
+    fn jpcc16(&mut self, n1: u8) -> u64 {
         // Conditional absolute jump
-        let p = self.r_16b_from_pc()?;
+        let p = self.r_16b_from_pc();
         let mut cycles = 8;
 
         if self.cpu.check_flag(n1 & 0b11) {
@@ -129,35 +129,35 @@ impl<S: Serial, A: Audio> GBState<S, A> {
             self.cpu.pc = p;
         }
 
-        Ok(cycles)
+        cycles
     }
 
-    fn call(&mut self) -> Result<u64, MemError> {
+    fn call(&mut self) -> u64 {
         // Unconditional function call
-        let p = self.r_16b_from_pc()?;
+        let p = self.r_16b_from_pc();
 
-        self.push(self.cpu.pc)?;
+        self.push(self.cpu.pc);
         self.cpu.pc = p;
 
-        Ok(24)
+        24
     }
 
-    fn callcc(&mut self, n1: u8) -> Result<u64, MemError> {
+    fn callcc(&mut self, n1: u8) -> u64 {
         // Conditional function call
-        let p = self.r_16b_from_pc()?;
+        let p = self.r_16b_from_pc();
         let mut cycles = 12;
 
         if self.cpu.check_flag(n1 & 0b11) {
             cycles += 12;
-            self.push(self.cpu.pc)?;
+            self.push(self.cpu.pc);
             self.cpu.pc = p;
         }
 
-        Ok(cycles)
+        cycles
     }
 
-    fn ret(&mut self) -> Result<u64, MemError> {
-        let res = self.pop()?;
+    fn ret(&mut self) -> u64 {
+        let res = self.pop();
 
         if res == 0 {
             println!("DEBUG: {:?}", self.cpu);
@@ -166,20 +166,20 @@ impl<S: Serial, A: Audio> GBState<S, A> {
 
         self.cpu.pc = res;
 
-        Ok(16)
+        16
     }
 
-    fn retcc(&mut self, n1: u8) -> Result<u64, MemError> {
+    fn retcc(&mut self, n1: u8) -> u64 {
         let mut cycles = 8;
         if self.cpu.check_flag(n1 & 0b11) {
             cycles += 12;
-            self.cpu.pc = self.pop()?;
+            self.cpu.pc = self.pop();
         }
 
-        Ok(cycles)
+        cycles
     }
 
-    fn ld00a(&mut self, n1: u8) -> Result<u64, MemError> {
+    fn ld00a(&mut self, n1: u8) -> u64 {
         // Load register A into or from memory pointed by rr (BC, DE or HL(+/-))
         // LD (rr), A
         // LD A, (rr)
@@ -190,10 +190,10 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         };
 
         if n1 & 0b001 == 1 {
-            self.cpu.r[reg::A as usize] = self.mem.r(self.cpu.r16(ptr_reg))?;
+            self.cpu.r[reg::A as usize] = self.mem.r(self.cpu.r16(ptr_reg));
         } else {
             self.mem
-                .w(self.cpu.r16(ptr_reg), self.cpu.r[reg::A as usize])?;
+                .w(self.cpu.r16(ptr_reg), self.cpu.r[reg::A as usize]);
         }
 
         if n1 & 0b110 == 0b100 {
@@ -204,39 +204,39 @@ impl<S: Serial, A: Audio> GBState<S, A> {
             self.cpu.w16(reg::HL, self.cpu.r16(reg::HL) - 1); // (HL-)
         }
 
-        Ok(8)
+        8
     }
 
-    fn inc8(&mut self, n1: u8) -> Result<u64, MemError> {
+    fn inc8(&mut self, n1: u8) -> u64 {
         // Increment 8 bit register
-        self.w_reg(n1, self.r_reg(n1)? + 1)?;
+        self.w_reg(n1, self.r_reg(n1) + 1);
         self.cpu.r[reg::F as usize] &= !(flag::N | flag::ZF | flag::H);
-        if self.r_reg(n1)? == 0 {
+        if self.r_reg(n1) == 0 {
             self.cpu.r[reg::F as usize] |= flag::ZF;
         }
 
-        if self.r_reg(n1)? & 0xf == 0x0 {
+        if self.r_reg(n1) & 0xf == 0x0 {
             self.cpu.r[reg::F as usize] |= flag::H;
         }
 
-        Ok(4)
+        4
     }
 
-    fn dec8(&mut self, n1: u8) -> Result<u64, MemError> {
+    fn dec8(&mut self, n1: u8) -> u64 {
         // Decrement 8 bit register
-        self.w_reg(n1, self.r_reg(n1)? - 1)?;
+        self.w_reg(n1, self.r_reg(n1) - 1);
         self.cpu.r[reg::F as usize] |= flag::N;
 
         self.cpu.r[reg::F as usize] &= !(flag::ZF | flag::H);
-        if self.r_reg(n1)? == 0 {
+        if self.r_reg(n1) == 0 {
             self.cpu.r[reg::F as usize] |= flag::ZF;
         }
 
-        if self.r_reg(n1)? & 0xf == 0xf {
+        if self.r_reg(n1) & 0xf == 0xf {
             self.cpu.r[reg::F as usize] |= flag::H;
         }
 
-        Ok(4)
+        4
     }
 
     fn inc16(&mut self, rr: u8) -> u64 {
@@ -301,8 +301,8 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         self.cpu.r[reg::A as usize] ^= 0xff;
     }
 
-    fn addsp8(&mut self) -> Result<u64, MemError> {
-        let n = self.r_8b_from_pc()? as i8;
+    fn addsp8(&mut self) -> u64 {
+        let n = self.r_8b_from_pc() as i8;
 
         self.cpu.sp = (self.cpu.sp as i32 + n as i32) as u16;
 
@@ -315,7 +315,7 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         if (self.cpu.sp as i32 + n as i32) & !0xffff != 0 {
             self.cpu.r[reg::F as usize] |= flag::CY;
         }
-        Ok(16)
+        16
     }
 
     fn add(&mut self, x: u8) {
@@ -473,9 +473,9 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         }
     }
 
-    fn rlc(&mut self, r_i: u8) -> Result<(), MemError> {
+    fn rlc(&mut self, r_i: u8) -> () {
         // ROTATE LEFT the input register
-        let mut n = self.r_reg(r_i)?;
+        let mut n = self.r_reg(r_i);
         self.cpu.r[reg::F as usize] &= !(flag::H | flag::N | flag::ZF | flag::CY);
         self.cpu.r[reg::F as usize] |= (n >> 7) << 4;
         n <<= 1;
@@ -483,9 +483,9 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         self.w_reg(r_i, n)
     }
 
-    fn rrc(&mut self, r_i: u8) -> Result<(), MemError> {
+    fn rrc(&mut self, r_i: u8) -> () {
         // ROTATE RIGHT the input register
-        let mut n = self.r_reg(r_i)?;
+        let mut n = self.r_reg(r_i);
         self.cpu.r[reg::F as usize] &= !(flag::H | flag::N | flag::ZF | flag::CY);
         self.cpu.r[reg::F as usize] |= (n & 1) << 4;
         n >>= 1;
@@ -493,10 +493,10 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         self.w_reg(r_i, n)
     }
 
-    fn rl(&mut self, r_i: u8) -> Result<(), MemError> {
+    fn rl(&mut self, r_i: u8) -> () {
         // ROTATE LEFT THROUGH CARRY the input register
         // (RLC IS ROTATE AND RL IS ROTATE THROUGH CARRY ! IT DOESN'T MAKE ANY SENSE !!)
-        let mut n = self.r_reg(r_i)?;
+        let mut n = self.r_reg(r_i);
         let carry = (self.cpu.r[reg::F as usize] & flag::CY) >> 4;
 
         self.cpu.r[reg::F as usize] &= !(flag::H | flag::N | flag::ZF | flag::CY);
@@ -506,9 +506,9 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         self.w_reg(r_i, n)
     }
 
-    fn rr(&mut self, r_i: u8) -> Result<(), MemError> {
+    fn rr(&mut self, r_i: u8) -> () {
         // ROTATE RIGHT THROUGH CARRY the input register
-        let mut n = self.r_reg(r_i)?;
+        let mut n = self.r_reg(r_i);
         let carry = (self.cpu.r[reg::F as usize] & flag::CY) >> 4;
 
         self.cpu.r[reg::F as usize] &= !(flag::H | flag::N | flag::ZF | flag::CY);
@@ -518,9 +518,9 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         self.w_reg(r_i, n)
     }
 
-    fn sla(&mut self, r_i: u8) -> Result<(), MemError> {
+    fn sla(&mut self, r_i: u8) -> () {
         // Shift left Arithmetic (b0=0) the input register
-        let mut n = self.r_reg(r_i)?;
+        let mut n = self.r_reg(r_i);
 
         self.cpu.r[reg::F as usize] &= !(flag::H | flag::N | flag::ZF | flag::CY);
         self.cpu.r[reg::F as usize] |= (n >> 7) << 4;
@@ -533,9 +533,9 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         self.w_reg(r_i, n)
     }
 
-    fn sra(&mut self, r_i: u8) -> Result<(), MemError> {
+    fn sra(&mut self, r_i: u8) -> () {
         // Shift right Arithmetic (b7=b7) the input register
-        let mut n = self.r_reg(r_i)?;
+        let mut n = self.r_reg(r_i);
 
         self.cpu.r[reg::F as usize] &= !(flag::H | flag::N | flag::ZF | flag::CY);
         self.cpu.r[reg::F as usize] |= (n & 0b1) << 4;
@@ -550,9 +550,9 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         self.w_reg(r_i, n)
     }
 
-    fn swap(&mut self, r_i: u8) -> Result<(), MemError> {
+    fn swap(&mut self, r_i: u8) -> () {
         // Swap the high nibble and low nibble
-        let mut n = self.r_reg(r_i)?;
+        let mut n = self.r_reg(r_i);
 
         let nibble_low = n & 0b1111;
         let nibble_high = n >> 4;
@@ -568,9 +568,9 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         self.w_reg(r_i, n)
     }
 
-    fn srl(&mut self, r_i: u8) -> Result<(), MemError> {
+    fn srl(&mut self, r_i: u8) -> () {
         // Shift right Logical (b7=0) the input register
-        let mut n = self.r_reg(r_i)?;
+        let mut n = self.r_reg(r_i);
 
         self.cpu.r[reg::F as usize] &= !(flag::H | flag::N | flag::ZF | flag::CY);
         self.cpu.r[reg::F as usize] |= (n & 0b1) << 4;
@@ -583,48 +583,48 @@ impl<S: Serial, A: Audio> GBState<S, A> {
         self.w_reg(r_i, n)
     }
 
-    fn bit(&mut self, n1: u8, n2: u8) -> Result<(), MemError> {
-        let z = (((self.r_reg(n2)? >> n1) & 1) ^ 1) << 7;
+    fn bit(&mut self, n1: u8, n2: u8) -> () {
+        let z = (((self.r_reg(n2) >> n1) & 1) ^ 1) << 7;
 
         self.cpu.r[reg::F as usize] &= !(flag::N | flag::ZF);
         self.cpu.r[reg::F as usize] |= flag::H | z;
-        Ok(())
+        ()
     }
 
-    fn set(&mut self, n1: u8, n2: u8) -> Result<(), MemError> {
-        self.w_reg(n2, self.r_reg(n2)? | (1 << n1))
+    fn set(&mut self, n1: u8, n2: u8) -> () {
+        self.w_reg(n2, self.r_reg(n2) | (1 << n1))
     }
 
-    fn res(&mut self, n1: u8, n2: u8) -> Result<(), MemError> {
-        self.w_reg(n2, self.r_reg(n2)? & !(1 << n1))
+    fn res(&mut self, n1: u8, n2: u8) -> () {
+        self.w_reg(n2, self.r_reg(n2) & !(1 << n1))
     }
 
     // I don't remember why I separated op00, op01, op10 and op11 AND I'M NOT GOING TO CHANGE IT
     // BECAUSE I LOVE CHAOS
 
-    fn op00(&mut self, n1: u8, n2: u8) -> Result<u64, MemError> {
+    fn op00(&mut self, n1: u8, n2: u8) -> u64 {
         // Dispatcher for the instructions starting with 0b00 based on their 3 LSB
         match n2 {
             0b000 => match n1 {
-                0b000 => Ok(4),
+                0b000 => 4,
                 0b001 => self.ldnnsp(),
                 0b010 => todo!("STOP"),
                 0b011 => self.jr8(),
                 _ => self.jrcc8(n1),
             },
             0b001 => match n1 {
-                0b001 | 0b011 | 0b101 | 0b111 => Ok(self.addhlrr(n1 >> 1)),
+                0b001 | 0b011 | 0b101 | 0b111 => self.addhlrr(n1 >> 1),
                 0b000 | 0b010 | 0b100 | 0b110 => {
-                    let p = self.r_16b_from_pc()?;
+                    let p = self.r_16b_from_pc();
                     self.ldrr16(n1 >> 1, p);
-                    Ok(12)
+                    12
                 }
                 _ => panic!(),
             },
             0b010 => self.ld00a(n1),
             0b011 => match n1 {
-                0b001 | 0b011 | 0b101 | 0b111 => Ok(self.dec16(n1 >> 1)),
-                0b000 | 0b010 | 0b100 | 0b110 => Ok(self.inc16(n1 >> 1)),
+                0b001 | 0b011 | 0b101 | 0b111 => self.dec16(n1 >> 1),
+                0b000 | 0b010 | 0b100 | 0b110 => self.inc16(n1 >> 1),
                 _ => panic!(),
             },
             0b100 => self.inc8(n1),
@@ -632,77 +632,77 @@ impl<S: Serial, A: Audio> GBState<S, A> {
             0b110 => self.ldr8(n1),
             0b111 => {
                 match n1 {
-                    0b000 => self.rlc(7)?,
-                    0b001 => self.rrc(7)?,
-                    0b010 => self.rl(7)?,
-                    0b011 => self.rr(7)?,
+                    0b000 => self.rlc(7),
+                    0b001 => self.rrc(7),
+                    0b010 => self.rl(7),
+                    0b011 => self.rr(7),
                     0b100 => self.daa(),
                     0b101 => self.cpl(),
                     0b110 => self.scf(),
                     0b111 => self.ccf(),
                     _ => panic!(),
                 };
-                Ok(4)
+                4
             }
             _ => panic!(),
         }
     }
 
-    fn op01(&mut self, n1: u8, n2: u8) -> Result<u64, MemError> {
+    fn op01(&mut self, n1: u8, n2: u8) -> u64 {
         // Dispatcher for the instructions starting with 0b01 (LD r,r and HALT)
         if n1 == 0b110 && n2 == 0b110 {
             self.mem.halt = true;
-            Ok(4)
+            4
         } else {
-            self.ldrr(n1, n2)?;
+            self.ldrr(n1, n2);
 
             if n1 == 0b110 || n2 == 0b110 {
-                Ok(8)
+                8
             } else {
-                Ok(4)
+                4
             }
         }
     }
 
-    fn op10(&mut self, n1: u8, n2: u8) -> Result<u64, MemError> {
+    fn op10(&mut self, n1: u8, n2: u8) -> u64 {
         // Dispatcher for the instructions starting with 0b10 (Arithmetic)
         match n1 {
-            0b000 => self.add(self.r_reg(n2)?),
-            0b001 => self.adc(self.r_reg(n2)?),
-            0b010 => self.sub(self.r_reg(n2)?),
-            0b011 => self.sbc(self.r_reg(n2)?),
-            0b100 => self.and(self.r_reg(n2)?),
-            0b101 => self.xor(self.r_reg(n2)?),
-            0b110 => self.or(self.r_reg(n2)?),
-            0b111 => self.cp(self.r_reg(n2)?),
+            0b000 => self.add(self.r_reg(n2)),
+            0b001 => self.adc(self.r_reg(n2)),
+            0b010 => self.sub(self.r_reg(n2)),
+            0b011 => self.sbc(self.r_reg(n2)),
+            0b100 => self.and(self.r_reg(n2)),
+            0b101 => self.xor(self.r_reg(n2)),
+            0b110 => self.or(self.r_reg(n2)),
+            0b111 => self.cp(self.r_reg(n2)),
             _ => panic!(),
         }
 
         if n2 == 0b110 {
-            Ok(8)
+            8
         } else {
-            Ok(4)
+            4
         }
     }
 
-    fn op11(&mut self, n1: u8, n2: u8) -> Result<u64, MemError> {
+    fn op11(&mut self, n1: u8, n2: u8) -> u64 {
         match n2 {
             0b000 => match n1 {
                 0b100 => {
-                    let n = self.r_8b_from_pc()?;
-                    self.ldnna(n as u16 | 0xff00)?;
-                    Ok(12)
+                    let n = self.r_8b_from_pc();
+                    self.ldnna(n as u16 | 0xff00);
+                    12
                 }
                 0b101 => self.addsp8(),
                 0b110 => {
-                    let n = self.r_8b_from_pc()?;
-                    self.ldann(n as u16 | 0xff00)?;
-                    Ok(12)
+                    let n = self.r_8b_from_pc();
+                    self.ldann(n as u16 | 0xff00);
+                    12
                 }
                 0b111 => {
-                    let n = self.r_8b_from_pc()?;
+                    let n = self.r_8b_from_pc();
                     self.ldrr16(reg::HL, n as u16 + self.cpu.sp);
-                    Ok(12)
+                    12
                 }
                 _ => self.retcc(n1 & 0b11),
             },
@@ -713,33 +713,33 @@ impl<S: Serial, A: Audio> GBState<S, A> {
 
                     self.ret()
                 }
-                0b101 => Ok(self.jphl()),
-                0b111 => Ok(self.ldsphl()),
+                0b101 => self.jphl(),
+                0b111 => self.ldsphl(),
                 _ => {
-                    let p = self.pop()?;
+                    let p = self.pop();
                     self.cpu.r[(n1 >> 1) as usize * 2 + 1] = (p & 0xff) as u8;
                     self.cpu.r[(n1 >> 1) as usize * 2] = (p >> 8) as u8;
-                    Ok(12)
+                    12
                 }
             },
             0b010 => match n1 {
                 0b100 => {
-                    self.ldnna(self.cpu.r[reg::C as usize] as u16 | 0xff00)?;
-                    Ok(8)
+                    self.ldnna(self.cpu.r[reg::C as usize] as u16 | 0xff00);
+                    8
                 }
                 0b101 => {
-                    let nn = self.r_16b_from_pc()?;
-                    self.ldnna(nn)?;
-                    Ok(16)
+                    let nn = self.r_16b_from_pc();
+                    self.ldnna(nn);
+                    16
                 }
                 0b110 => {
-                    self.ldann(self.cpu.r[reg::C as usize] as u16 | 0xff00)?;
-                    Ok(8)
+                    self.ldann(self.cpu.r[reg::C as usize] as u16 | 0xff00);
+                    8
                 }
                 0b111 => {
-                    let nn = self.r_16b_from_pc()?;
-                    self.ldann(nn)?;
-                    Ok(16)
+                    let nn = self.r_16b_from_pc();
+                    self.ldann(nn);
+                    16
                 }
                 _ => self.jpcc16(n1 & 0b11),
             },
@@ -749,15 +749,15 @@ impl<S: Serial, A: Audio> GBState<S, A> {
                 0b011 | 0b100 | 0b101 => unimplemented!(),
                 0b010 => {
                     self.cpu.print_debug();
-                    Ok(4)
+                    4
                 }
                 0b110 => {
                     self.mem.ime = false;
-                    Ok(4)
+                    4
                 }
                 0b111 => {
                     self.mem.ime = true;
-                    Ok(4)
+                    4
                 }
                 _ => panic!(),
             },
@@ -768,12 +768,12 @@ impl<S: Serial, A: Audio> GBState<S, A> {
                 _ => {
                     let value = self.cpu.r[(n1 >> 1) as usize * 2 + 1] as u16
                         | ((self.cpu.r[(n1 >> 1) as usize * 2] as u16) << 8);
-                    self.push(value)?;
-                    Ok(16)
+                    self.push(value);
+                    16
                 }
             },
             0b110 => {
-                let p = self.r_8b_from_pc()?;
+                let p = self.r_8b_from_pc();
 
                 match n1 {
                     0b000 => self.add(p),
@@ -786,21 +786,21 @@ impl<S: Serial, A: Audio> GBState<S, A> {
                     0b111 => self.cp(p),
                     _ => panic!(),
                 }
-                Ok(8)
+                8
             }
             0b111 => {
                 let p = n1 << 3;
 
-                self.push(self.cpu.pc)?;
+                self.push(self.cpu.pc);
                 self.cpu.pc = p as u16;
-                Ok(16)
+                16
             } // RST
             _ => panic!(),
         }
     }
 
-    fn op_bitwise(&mut self) -> Result<u64, MemError> {
-        let p = self.r_8b_from_pc()?;
+    fn op_bitwise(&mut self) -> u64 {
+        let p = self.r_8b_from_pc();
         let opcode = p >> 6;
         let n1 = p >> 3 & 0b111;
         let n2 = p & 0b111;
@@ -821,16 +821,16 @@ impl<S: Serial, A: Audio> GBState<S, A> {
             0b10 => self.res(n1, n2),
             0b11 => self.set(n1, n2),
             _ => panic!(),
-        }?;
+        };
         if n2 == 0b110 {
-            Ok(16)
+            16
         } else {
-            Ok(8)
+            8
         }
     }
 
-    pub fn exec_opcode(&mut self) -> Result<u64, MemError> {
-        let opcode = self.mem.r(self.cpu.pc)?;
+    pub fn exec_opcode(&mut self) -> u64 {
+        let opcode = self.mem.r(self.cpu.pc);
 
         if self.is_debug {
             println!(